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1 of 21 rev: 071105 features ? real-time clock keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years ? 512k x 8 nv sram directly replaces volatile static ram or eeprom ? embedded lithium energy cell maintains calendar operation and retains ram data ? watch function is transparent to ram operation ? month and year determine the number of days in each month; valid up to 2100 ? over 10 years of data retention in the absence of power ? full 10% operating range ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? dip module only ? standard 32-pin jedec pinout ? upward comparable with the ds1248 ? powercap ? module board only ? surface mountable package for direct connection to powercap containing battery and crystal ? replaceable battery (powercap) ? pin-for-pin compatible with other densities of ds124xp phantom clocks ? underwriters laboratory (ul) recognized ( www.maxim-ic.com/qa/info/ul/ ) ? available in lead-free package pin configurations powercap is a registered trademark of maxim integrated products, inc. ds1251/ds1251p 4096k nv sram with phantom clock www.maxim-ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 encapsulated package 740-mil flush a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 a17 w e a13 a8 a9 a11 o e a10 c e dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 a1 8/ rs t dq2 gnd 15 16 18 17 dq4 dq3 d s 12 5 1 1 r st 2 3 a15 a16 n.c. v cc w e o e c e dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17 a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 x1 gnd v bat x2 powercap module board (uses ds9034pcx powercap) ds1251p top view
ds1251/ds1251p 2 of 21 ordering information part t temp range temp range voltage range (v) voltage range (v) pin-package pin-package top mark top mark ds1251w-120 0c to +70c 3.3 32 emod (0.740a) ds1251w-120 ds1251w-120+ 0c to +70c 3.3 32 emod (0.740a) ds1251w-120+ DS1251W-120IND -40c to +85c 3.3 32 emod (0.740a) ds1251w-12i ind DS1251W-120IND+ -40c to +85c 3.3 32 emod (0.740a) ds1251w-12i+ind ds1251wp-120 0c to +70c 3.3 34 powercap* ds1251wp-120 ds1251wp-120+ 0c to +70c 3.3 34 powercap* ds1251wp-120+ ds1251wp-120ind -40c to +85c 3.3 34 powercap* ds1251wp-120ind ds1251wp-120ind+ -40c to +85c 3.3 34 powercap* ds1251wp-120ind+ ds1251y-70 0c to +70c 5.0 32 emod (0.740a) ds1251y-070 ds1251y-70+ 0c to +70c 5.0 32 emod (0.740a) ds1251y-070+ ds1251yp-70 0c to +70c 5. 0 34 powercap* ds1251yp-070 ds1251yp-70+ 0c to +70c 5. 0 34 powercap* ds1251yp-070+ ds1251yp-70ind -40c to +85c 5.0 34 powercap* ds1251yp-070 ind ds1251yp-70ind+ -40c to +85c 5.0 34 powercap* ds1251yp-070+ind + denotes a lead(pb)-free/rohs-compliant device. * ds9034pcx (powercap) required. must be ordered separately. pin description pin edip powercap name function 1 1 rst active-low reset input. this pin has an internal pullup resistor connected to v cc . 1 34 a18 2 3 a16 3 32 a14 4 30 a12 5 25 a7 6 24 a6 7 23 a5 8 22 a4 9 21 a3 10 20 a2 11 19 a1 12 18 a0 23 28 a10 25 29 a11 26 27 a9 27 26 a8 28 31 a13 30 33 a17 31 2 a15 address inputs 13 16 dq0 14 15 dq1 15 14 dq2 17 13 dq3 18 12 dq4 19 11 dq5 20 10 dq6 21 9 dq7 data in/data out
ds1251/ds1251p 3 of 21 pin description (continued) pin edip powercap name function 22 8 ce active-low chip-enable input 24 7 oe active-low output-enable input 29 6 we active-low write-enable input 32 5 v cc power-supply input ? 4 n.c. no connection 16 17 gnd ground description the ds1251 4096k nv sram with phantom clock is a fu lly static nonvolatile ra m (organized as 512k words by 8 bits) with a built-in re al-time clock. the ds1251y has a se lf-contained lithium energy source and control circuitry, which constantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switch ed on and write protection is unconditionally enabled to prevent garbled da ta in both the memory and real-time clock. the phantom clock provides timekeeping informati on including hundredths of seconds, seconds, minutes, hours, days, dates, months, and years. the date at the end of the month is automatically adjusted for months with fewer than 31 days, in cluding correction for leap years. th e phantom clock ope rates in either 24-hour or 12-hour format with an am/pm indicator. packages the ds1251 is available in two packages: 32-pin dip and 34-pin powercap module. the 32-pin dip style module integrates the crystal, lithium energy source, and silicon in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1251p after the completion of the surface mount process. mounting the powercap af ter the surface mount process prevents damage to the crystal and ba ttery because of the high temperatures required for solder reflow. the powercap is keyed to preven t reverse insertion. the powercap module board and powercap are ordered separately an d shipped in separate containers. ram read mode the ds1251 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address sp ecified by the 19 address inputs (a0? a18) defines which of the 512k bytes of data is to be accessed. va lid data will be available to the eight data-output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times and states are also satisfied. if oe and ce access times are not satisfied , then data access must be measured from the later occurring signal ( c e or o or e ) and the limiting parameter is either t co f ce or t oe for oe , rather than address acces s. ram write mode the ds1251 is in the write mode whenever the we and ce signals are in the active (low) state after address inputs are stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is termin ated by the earlier rising edge of ce or we . all address inputs must
ds1251/ds1251p 4 of 21 be kept valid throughout the write cycle. we mu return to the high stat e for a minimum recovery time (t wr ) before another cycle can be initiated. the st oe control signal s hould be kept ina ve (hi ) during write cles to avoid bus contention. however, if the output b c ti gh cy us has been enabled ( ce and oe active) we then will disable the outputs in t odw from its falling edge. y. rtc peration and sram data are m aintained from the battery until v is returned to nominal levels. c operation and sram data are ma intained f rom the battery until v cc is returned to ominal levels. cc is powered down. er data on q0. all accesses that o ccur prior to recognition of the 64-bit patte rn are directed to memory. ad or write cycles either extract or update data in the hantom clock, and memory access is inhibited. of na data retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power-fail point, v pf (point at which write protection occurs), the internal clock registers and sram ar e blocked from any access. when v cc falls below the battery switch point, v so (battery supply level), device power is switched from the v cc pin to the backup batter o cc the 3.3v device is fully accessib le and data can be written or read only when v cc is greater than v pf. when v cc falls below the power-fail point, v pf , access to the device is inhibited. if v pf is less than v bat, the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v bat . rt n all control, data, and address signa ls m ust be powered down when v phantom clock operation communication with the phantom cloc k is established by pattern recogn ition on a serial bit stream of 64 bits, which must be matched by executing 64 consecu tive write cycles contai ning the prop d after recognition is established, the next 64 re p data transfer to and from the timekeeping function is accomplished with a serial bit stream under control chip e ble, output enable, and write enable. initially, a read cycl e to any memory location using the ce and oe control of the phantom clock starts the pattern recognition se quence by moving a pointer to first b f the 64-bit comparis on register. next, 64 consecutive writ e cycles are executed using the the it o ce and we control of the smartwatch. these 64 write cy cles are used only to gain access to the phantom clock. therefore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one address location in ram as a phantom clock scratch pad. when the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. if a match is found, the pointer incremen ts to the next location of the comparison register and awaits the next write cycle. if a ma tch is not found, the pointer does not advance and all subsequent write cycles are ignored . if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described above until all the bits in the compar ison register have been matched (figure 1). with a correct match for 64 bits, th e phantom clock is enabled and data transfer to or
ds1251/ds1251p 5 of 21 pha e from the timekeeping registers can proceed. the next 64 cycles will cause the ntom clock to either receive or transmit data on dq0, depending on the level of th oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cyc les without interrupting the pattern cognition sequence or data transf er sequence to the phantom clock. bits within a register could produce erroneous results. these re ad/write reg isters are defined in igure 2. by stepping through all eight registers, starting with bit 0 of gister 0 and ending with bit 7 of register 7. hantom clock register definition figure 1 re phantom clock regi ster information the phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64-bit pattern re cognition sequence has been completed. when updating the phantom clock registers, each register must be handled in groups of 8 bits. writing and reading individual f data contained in the phantom clock register is in binary-coded decimal format (bcd). reading and writing the registers is always accomplished re p note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a 3, 5c. the odds of this pattern being accidentally duplicated and causing inadver tent entry to the phantom clock is less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb.
ds1251/ds1251p 6 of 21 phantom clock register definition figure 2 am/pm/12/24 mode bit 7 of the hours register is defi ned as the 12-hour or 24-hour mode -select bit. when high, the 12-hour mode is selected. in the 12-hour mo de, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the rst and oscillator functions. bit 4 controls the (pin 1). when the bit is set to logic 1, the rst input pin is ignored. when the rst rst rst bit is set to logic 0, a low input on the rst pin will cause the phantom clock to abort data transfer without changing data in the watch registers. bit 5 co ntrols the oscillator. when set to lo gic 1, the oscillator is off. when set to logic 0, the oscillator turns on and the watch beco mes operational. these bits are shipped from the factory set to a logic 1. zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits, which will always read logic 0. when writing these locations, either a logic 1 or 0 is acceptable.
ds1251/ds1251p 7 of 21 battery longevity the ds1251 has a lithium power source that is designed to provide en ergy for clock activity, and clock and ram data retention when the v cc supply is not present. the capabilit y of this internal power supply is sufficient to power the ds1251 continuously for the lif e of the equipment in wh ich it is installed. for specification purposes, the life expe ctancy is 10 years at +25 ? c with the internal clock oscillator running in the absence of v cc power. each ds1251 is shipped from dalla s semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery-backup operation. actual life expectancy of the ds1251 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. clock accuracy (dip module) the ds1251 is guaranteed to k eep time accuracy to within ? 1 minute per month at +25 ? c. the clock is calibrated at the factory by dallas semiconductor us ing special calibration nonvolatile tuning elements. the ds1251 does not require additional calibration and temperature deviations will have a negligible effect in most applications. for this reason, methods of field clock calibration are not available and not necessary. clock accuracy (p owercap module) the ds1251p and ds9034pcx are each individually te sted for accuracy. once mounted together, the module is guaranteed to k eep time accuracy to within ? 1.53 minutes per month (35ppm) at +25 ? c.
ds1251/ds1251p 8 of 21 absolute maxi mum ratings voltage range on any pin relative to ground?????????????????..-0.3v to +6.0v soldering temperature range??????????????..+260c for 10 seconds (dip) (note 13) see ipc/jedec standard j-std-020a for surface-mount devices this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. operating range range temp range (noncondensing) v cc (v) commercial 0c to +70c 3.3 ? 10% or 5 ? 10% industrial -40c to +85c 3.3 ? 10% or 5 ? 10% recommended dc oper ating conditions (t a = over the operating range.) parameter symbol min typ max units notes v cc = 5v 10% 2.2 v cc + 0.3v logic 1 voltage all inputs v cc = 3.3v 10% v ih 2.0 v cc + 0.3v v 11 v cc = 5v 10% -0.3 +0.8 logic 0 voltage all inputs v cc = 3.3v 10% v il -0.3 +0.6 v 11
ds1251/ds1251p 9 of 21 dc electrical characteristics (t a = over the operating range.) (5v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 ? a 12 i/o leakage current ce ? v ih v cc i io -1.0 +1.0 ? a output current at 2.4v i oh -1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5 10 ma standby current ce = v cc - 0.5v i ccs2 3.0 5.0 ma operating current t cyc = 70ns i cc01 85 ma write protection voltage v pf 4.25 4.37 4.50 v 11 battery switchover voltage v so v bat v 11 dc electrical characteristics (t a = over the operating range.) (3.3v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 ? a 12 i/o leakage current ce ? v ih v cc i io -1.0 +1.0 ? a output current at 2.4v i oh -1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5 7 ma standby current ce = v cc - 0.5v i ccs2 2.0 3.0 ma operating current t cyc = 70ns i cc01 50 ma write protection voltage v pf 2.80 2.97 v 11 battery switchover voltage v so v bat or v pf v 11 capacitance (t a = +25 ?c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf
ds1251/ds1251p 10 of 21 memory ac electrical characteristics (t a = over the operating range.) (5v) ds1251y-70 parameter symbol min max units notes read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high-z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 50 ns 3 address setup time t aw 0 ns write recovery time t wr 0 ns output high-z from we t odw 25 ns 5 output active from we t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time from we t dh 5 ns 4
ds1251/ds1251p 11 of 21 phantom clock ac electrical characteristics (t a = over the operating range.) (5v) parameter symbol min typ max units notes read cycle time t rc 65 ns ce access time t co 55 ns oe access time t oe 55 ns ce to output low-z t coe 5 ns oe to output low-z t oee 5 ns ce to output high-z t od 25 ns 5 oe to output high-z t odo 25 ns 5 read recovery t rr 10 ns write cycle time t wc 65 ns write pulse width t wp 55 ns 3 write recovery t wr 10 ns 10 data setup time t ds 30 ns 4 data hold time t dh 0 ns 4 ce pulse width t cw 60 ns rst pulse width t rst 65 ns power-down/power-up timing (t a = over the operating range.) (3.3v) parameter symbol min typ max units notes ce at v ih before power-down t pd 0 ? s v cc slew from v pf(max) to v pf(min) (ce at v pf ) t f 300 ? s v cc slew from v pf(min) to v so t fb 10 ? s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t r 0 ? s ce at v ih after power-up t rec 1.5 2.5 ms (t a = +25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoot s of any amplitude allowed when device is in battery-backup mode.
ds1251/ds1251p 12 of 21 memory ac electrical characteristics (t a = over the operating range.) (3.3v) ds1251w-120 parameter symbol min max units notes read cycle time t rc 120 ns access time t acc 120 ns oe to output valid t oe 60 ns ce to output valid t co 120 ns oe or ce to output active t coe 5 ns 5 output high-z from deselection t od 40 ns 5 output hold from address change t oh 5 ns write cycle time t wc 120 ns write pulse width t wp 90 ns 3 address setup time t aw 0 ns write recovery time t wr 20 ns 10 output high-z from we t odw 40 ns 5 output active from we t oew 5 ns 5 data setup time t ds 50 ns 4 data hold time from we t dh 20 ns 4 phantom clock ac electrical characteristics (t a = over the operating range.) (3.3v) parameter symbol min typ max units notes read cycle time t rc 120 ns ce access time t co 100 ns oe access time t oe 100 ns ce to output low-z t coe 5 ns oe to output low-z t oee 5 ns ce to output high-z t od 40 ns 5 oe to output high-z t odo 40 ns 5 read recovery t rr 20 ns write cycle time t wc 120 ns write pulse width t wp 100 ns 3 write recovery t wr 20 ns 10 data setup time t ds 45 ns 4 data hold time t dh 0 ns 4 ce pulse width t cw 105 ns rst pulse width t rst 120 ns
ds1251/ds1251p 13 of 21 power-down/power-up timing (t a = over the operating range.) (3.3v) parameter symbol min typ max units notes ce at v ih before power-down t pd 0 ? s v cc slew from v pf(max) to v pf(min) (ce at v ih ) t f 300 ? s v cc slew from v pf(max) to v pf(min) (ce at v ih ) t r 0 ? s ce at v ih after power-up t rec 1.5 2.5 ms (t a = +25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undersh oots of any amplitude allowed when device is in battery-backup mode.
ds1251/ds1251p 14 of 21 memory read cycle (note 1) memory write cycle 1 (notes 2, 6, and 7)
ds1251/ds1251p 15 of 21 memory write cycle 2 (notes 2 and 8) reset for phantom clock read cycle to phantom clock
ds1251/ds1251p 16 of 21 write cycle to phantom clock power-down/power-up condition ( 5v )
ds1251/ds1251p 17 of 21 power-down/power-up condition ( 3.3v )
ds1251/ds1251p 18 of 21 ac test conditions output load: 50pf + 1ttl gate input pulse levels: 0 to 3v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) we is high for a read cycle. 2) oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. 3) t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4) t dh , t ds are measured from the earlier of ce or we going high. 5) these parameters are sampled with a 50pf load and ar e not 100% tested. 6) if the ce low transition occurs simultane ously with or later than the we low transition in write cycle 1, the output buffers remain in a hi gh-impedance state during this period. 7) if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high-impeda nce state during this period. 8) if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9) the expected t dr is defined as cumulative time in the absence of v cc with the clock oscillator running. 10) t wr is a function of the la tter occurring edge of we or ce . 11) voltages are referenced to ground. 12) rst (pin 1) has an internal pullup resistor. 13) real-time clock modules can be successfully processed through conventional wave-soldering techniques as long as temperatur e exposure to the lithium energy s ource contained within does not exceed +85c. post-solder cleaning with water-w ashing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap: 1) dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the labe l side up (?live-bug?). 2) hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than three seconds. ? to solder, apply flux to the pad, heat the lead frame pad, and apply solder. to remove the part, apply flux, heat the lead frame pa d until the solder reflows, and use a solder wick to remove solder.
ds1251/ds1251p 19 of 21 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/package s . package type package code document no. 32 edip mdt32+5 21-0245 34 pwrcp pc2+5 21-0246 ds1251p pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: maxim recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live- bug?). hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than three seconds. to solder, apply flux to the pad, heat the lead frame pad, and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove solder.
ds1251/ds1251p 20 of 21 ds1251p with ds9034pcx attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 components and placement may vary from each device type
ds1251/ds1251p 21 of 21 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. recommended powercap module land pattern pkg inches dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 -

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